Reuse of host hibernation storage space by memory controller

ABSTRACT

A method for data storage includes, in a host system that operates alternately in a normal state and a hibernation state, reserving a hibernation storage space in a non-volatile storage device for storage of hibernation-related information in preparation for entering the hibernation state. While the host system is operating in the normal state, a storage task other than storage of the hibernation-related information is performed using at least a portion of the reserved hibernation storage space.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 12/880,101, now U.S. Pat. No. 8,694,814, filed Sep. 12, 2010 which claims the benefit of U.S. Provisional Patent Application 61/293,676, filed Jan. 10, 2010, and U.S. Provisional Patent Application 61/324,429, filed Apr. 15, 2010, whose disclosures are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and particularly to reusing memory space allocated for storing hibernation data.

BACKGROUND OF THE INVENTION

Some computing devices, such as notebook computers, support a hibernation state. The hibernation state is typically a low power consumption state that preserves the state of the computing device and its applications so that operation can later resume without having to restart the applications or the operating system. When preparing to enter hibernation, the computing device stores application data and other information in non-volatile memory. When returning from hibernation to normal operation, the computing device retrieves the stored information, and resumes operation from the point at which it began to hibernate.

Some storage devices, such as Solid-State Disks (SSD), use arrays of analog memory cells for non-volatile data storage. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.

SUMMARY OF THE INVENTION

An embodiment of the present invention that is described herein provides a method for data storage, including:

in a host system that operates alternately in a normal state and a hibernation state, reserving a hibernation storage space in a non-volatile storage device for storage of hibernation-related information in preparation for entering the hibernation state; and

while the host system is operating in the normal state, performing a storage task other than storage of the hibernation-related information using at least a portion of the reserved hibernation storage space.

In some embodiments, the non-volatile storage device includes multiple memory blocks, and performing the storage task includes allocating over-provisioning memory overhead for copying valid data from partially-programmed memory blocks so as to produce memory blocks ready for erasure, such that at least some of the over-provisioning memory overhead is allocated in the hibernation storage space. In a disclosed embodiment, performing the storage task includes caching the user data accepted from the host system in the hibernation storage space, and subsequently copying the cached user data to storage locations outside the hibernation storage space. In an embodiment, caching the user data includes writing the user data to the hibernation storage space at a first storage throughput, and copying the cached user data includes storing the user data outside the hibernation storage space at a second storage throughput that is lower than the first storage throughput.

In some embodiments, reserving the hibernation storage space includes allocating a set of the storage locations by the host system to serve as the hibernation storage space, and performing the storage task includes identifying at least part of the storage locations in the set, and performing the storage task using the identified storage locations. In an embodiment, identifying the storage locations in the set includes receiving a notification from the host system indicative of the set of storage locations. In an alternative embodiment, identifying the storage locations in the set includes automatically identifying a file holding the hibernation-related information in a file system of the host system. In yet another embodiment, the method includes, in preparation for entering the hibernation state, receiving the hibernation-related information from the host system using one or more dedicated hibernation write commands, and identifying the storage locations in the set includes detecting the storage locations written to using the dedicated hibernation write commands.

In a disclosed embodiment, the method includes detecting that the host system is preparing to enter the hibernation state. In an embodiment, the method includes switching to store the hibernation-related information using a high-speed storage configuration responsively to detecting that the host system is preparing to enter the hibernation state. In another embodiment, detecting that the host system is preparing to enter the hibernation state includes detecting one or more dedicated hibernation write commands received from the host system. Alternatively, detecting that the host system is preparing to enter the hibernation state includes detecting one or more write commands to storage locations belonging to the hibernation storage space. Further alternatively, detecting that the host system is preparing to enter the hibernation state includes receiving a notification from the host system indicating a preparation to enter the hibernation state.

In some embodiments, the method includes detecting that the host system is preparing to exit the hibernation state. In an embodiment, detecting that the host system is preparing to exit the hibernation state includes detecting one or more read commands from storage locations belonging to the hibernation storage space. In an alternative embodiment, detecting that the host system is preparing to exit the hibernation state includes receiving a notification from the host system indicating a preparation to exit the hibernation state.

In still another embodiment, performing the storage task includes using at least the portion of the hibernation storage space only responsively to verifying that the hibernation-related information is invalid. In another embodiment, the method includes marking the hibernation-related information as invalid after the host system exits from the hibernation state and retrieves the hibernation-related information from the non-volatile storage device. In yet another embodiment, the method includes, in preparation for entering the hibernation state, storing part of the hibernation-related information in the portion of the hibernation storage space used for performing the storage task.

In some embodiments, the method includes writing user data at a first throughput, and, in preparation for entering the hibernation state, writing the hibernation-related information to the hibernation storage space at a second throughput, higher than the first throughput. In an embodiment, the method includes, in preparation for entering the hibernation state, compressing the hibernation-related information and storing the compressed hibernation-related information in the hibernation storage space. In another embodiment, the method includes receiving a notification from the host system indicating that the host system is preparing to enter the hibernation state, and vacating the portion of the hibernation storage space in response to the notification.

There is additionally provided, in accordance with an embodiment of the present invention, a method for data storage, including:

accepting from a host system data, which belongs to one or more files that are organized in accordance with a file system, and storing the data in a non-volatile storage device;

processing the data stored in the non-volatile storage device so as to identify a file that was marked as invalid by the file system of the host system; and

releasing a memory space occupied by the identified file in the non-volatile storage device.

There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

a non-volatile memory; and

a memory controller, which is configured to store data for a host system that operates alternately in a normal state and a hibernation state, to reserve a hibernation storage space in the non-volatile memory for storage of hibernation-related information in preparation for entering the hibernation state, and, while the host system is operating in the normal state, to perform a storage task other than storage of the hibernation-related information using at least a portion of the reserved hibernation storage space.

There is further provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

a non-volatile memory; and

a memory controller, which is configured to accept from a host system data belonging to one or more files that are organized in accordance with a file system, to store the data in the non-volatile storage device, to process the data stored in the non-volatile storage device so as to identify a file that was marked as invalid by the file system of the host system, and to release a memory space occupied by the identified file in the non-volatile storage device.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a computing device that supports a hibernation state, in accordance with an embodiment of the present invention;

FIG. 2 is a diagram that schematically illustrates a hibernation storage space used for storage management during normal operation, in accordance with an embodiment of the present invention; and

FIG. 3 is a flow chart that schematically illustrates a method for operating a Solid-State Disk (SSD) in a computing device that supports hibernation, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS Overview

Embodiments of the present invention that are described herein provide improved methods and systems for operating non-volatile storage devices (e.g., Solid-State Disks—SSD) in computing systems that support a hibernation state. The term “hibernation state” refers to any operational state in which the computing system reduces its energy consumption by deactivating at least part of its circuitry, and backs-up certain information to non-volatile storage before entering this operational state. Operational states or modes that are sometimes referred to as “standby,” “sleep” or “battery-save” are also regarded herein as hibernation states.

In some embodiments, a host system stores data in a non-volatile storage device, which comprises a non-volatile memory and a memory controller. The host system supports a hibernation state and a normal state, and may alternate between the two states. When preparing to enter the hibernation state, the host system creates a hibernation file containing hibernation-related information, and stores the hibernation file in a reserved hibernation storage space in the non-volatile memory. When returning from the hibernation state to the normal stage, the host system retrieves the hibernation file and uses the hibernation-related information to resume normal operation.

In some embodiments of the present invention, the memory controller reuses the reserved hibernation storage space for storage tasks other than storing the hibernation-related information while the host system is operating in the normal state. In some embodiments, the memory controller accepts user data for storage from the host system, and stores the user data in storage locations that are outside the hibernation storage space. The memory controller manages the storage of the user data, however, using at least part of the hibernation storage space. The memory controller may use the hibernation storage space for various functions. Several examples of such uses, e.g., over-provisioning and binary caching, are described herein.

In some embodiments, the hibernation storage space is reserved by the host system, and the memory controller automatically identifies at least some storage locations belonging to the hibernation storage space, and uses the identified locations for storage management or other tasks.

In many practical systems, the hibernation storage space occupies a considerable portion of the non-volatile storage device, but is largely unused during normal operation. The disclosed techniques enable the memory controller to exploit this storage resource, and to improve storage speed and reliability by reusing it.

System Description

FIG. 1 is a block diagram that schematically illustrates a host system 20 that supports a hibernation state, in accordance with an embodiment of the present invention. In the present example, system 20 comprises a mobile computing device such as a notebook or laptop computer. Alternatively, the methods and systems described herein can be used in other computing devices such as Personal Digital Assistants (PDAs), in mobile communication terminals such as mobile phones, or in any other suitable host system.

Host system 20 comprises a host processor 24. The host processor typically runs a certain Operating System (OS), and may run any desired number of software applications. Host system 20 comprises a Random Access Memory (RAM) 28, in which host processor 24 stores data, program instructions and/or any other information. In addition, host system 20 comprises a non-volatile storage device, in the present example a Solid-State Disk (SSD) 32. SSD 32 comprises a host interface 36 for communicating with host processor 24, an SSD controller 40, and one or more non-volatile memory devices 44. Each memory device 44 comprises an array 48 of multiple analog memory cells 52. A Read/Write (R/W) unit 56 writes data into memory cells 52 of array 48, and retrieves data from the memory cells.

In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array 48 may comprise analog memory cells of any kind, such as, for example, NAND, NOR and Charge Trap Flash (CTF) Flash cells, phase change RAM (PRAM, also referred to as Phase Change Memory—PCM), Nitride Read Only Memory (NROM), Ferroelectric RAM (FRAM), magnetic RAM (MRAM) and/or Dynamic RAM (DRAM) cells. Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

NROM cells are described by Eitan et al., in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24^(th) International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.

The charge levels stored in memory cells 52 and/or the analog voltages or currents written into and read out of the memory cells are referred to herein collectively as analog values or storage values. The storage values may comprise threshold voltages, electrical charge levels, or any other suitable kind of storage values. R/W unit 56 stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values into the cell. Typically, R/W unit 56 converts data for storage in the memory device to analog storage values, and writes them into memory cells 52. When reading data out of array 48, R/W unit 56 converts the storage values of memory cells 52 into digital samples. Data is typically written to and read from the memory cells in groups that are referred to as pages. The R/W unit erases a block of cells 52 by applying one or more negative erasure pulses to the cells.

Some or all of the functions of SSD controller 40 may be implemented in hardware. Alternatively, SSD controller 40 may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements. In some embodiments, SSD controller 40 comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.

The configuration of FIG. 1 is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention have been omitted from the figure for clarity. In the example system configuration shown in FIG. 1, memory devices 44 and SSD controller 40 are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory devices and the SSD controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC), and may be interconnected by an internal bus. Further alternatively, some or all of the SSD circuitry may reside on the same die on which one or more of the memory devices are disposed. Further alternatively, some or all of the functionality of SSD controller 40 can be implemented in software and carried out by host processor 24. In some embodiments, host processor 24 and SSD controller 40 may be fabricated on the same die, or on separate dies in the same device package.

In an example configuration of array 48, memory cells 52 are arranged in multiple rows and columns, and each memory cell comprises a floating-gate transistor. The gates of the transistors in each row are connected by word lines, and the sources of the transistors in each column are connected by bit lines. The memory array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Pages are sometimes sub-divided into sectors. In some embodiments, each page comprises an entire row of the array. In alternative embodiments, each row (word line) can be divided into two or more pages. For example, in some devices each row is divided into two pages, one comprising the odd-order cells and the other comprising the even-order cells. In a typical implementation, a two-bit-per-cell memory device may have four pages per row, a three-bit-per-cell memory device may have six pages per row, and a four-bit-per-cell memory device may have eight pages per row.

Erasing of cells is usually carried out in blocks that contain multiple pages. Typical memory devices may comprise several thousand erasure blocks. In some two-bit-per-cell MLC devices, each erasure block is on the order of thirty-two word lines, each comprising several tens of thousands of memory cells. Each word line of such a device is often partitioned into four pages (odd/even order cells, least/most significant bit of the cells). Three-bit-per cell devices having thirty-two word lines per erasure block would have 192 pages per erasure block, and four-bit-per-cell devices would have 256 pages per block. Alternatively, other block sizes and configurations can also be used. Some memory devices comprise two or more separate memory cell arrays, often referred to as planes. Since each plane has a certain “busy” period between successive write operations, data can be written alternately to the different planes in order to increase programming speed.

Typically, host processor 24 reads and writes data in SSD 32 by specifying logical addresses of the data (e.g., using Logical Block Addressing—LBA). SSD controller 40 translates the logical addresses into respective physical storage locations in memory devices 44. Typically, the host processor is unaware of the actual physical storage locations in which the data is stored, and the logical-to-physical translation may change over time.

Using Hibernation Storage Space for Storage Management Functions

Host system 20 supports at least two operational states—a normal state and a hibernation state. When operating in the normal state, host processor 24, RAM 28 and SSD 32 are connected to electrical power and are fully operational. When operating in the hibernation state, at least some of the elements of host system 20 are deactivated in order to save power. When preparing to enter the hibernation state, host processor 24 sends hibernation-related information for storage in SSD 32. Upon returning to normal operation, the hibernation-related information enables the host processor to resume operation of host system 20 from the point it began hibernating. The hibernation-related information may comprise, for example, the state and variables of the operating system and of the applications running on processor 24, information stored in RAM 28, or any other suitable information.

In some embodiments, when preparing to enter hibernation, the host processor builds a hibernation file and stores the hibernation file in SSD 32 (main storage). When returning from the hibernation state to the normal state, the host processor retrieves the hibernation file from the SSD, extracts the hibernation-related information from the file, and resumes the host system operation using the extracted information.

Typically, host processor 24 pre-assigns and reserves a certain logical storage space in SSD 32 (i.e., a certain set of logical addresses or LBAs) for the hibernation file. This space is referred to herein as “hibernation storage space.” During normal operation, the user data is not stored in this space. The hibernation storage space is reserved in order to ensure that sufficient space is available for storing the hibernation file when necessary. Any suitable memory size may be reserved. Since the hibernation storage space is specified in terms of logical addresses, the physical storage location of the hibernation file in memory devices 44 may change over time. Typically although not necessarily, the hibernation storage space is on the order of the size of RAM 28.

As can be appreciated, the hibernation storage space may occupy a considerable portion of the total storage capacity of SSD 32. (In an example embodiment, the total RAM size is on the order of 2-4 GB, and the SSD main storage capacity is on the order of 64-256 GB. In alternative embodiments, any other suitable RAM and SSD sizes can also be used.) The hibernation storage space is accessed when preparing to enter hibernation and upon returning from hibernation to normal operation, and is otherwise mostly unused during normal operation.

In some embodiments, SSD controller 40 uses at least part of the hibernation storage space in SSD 32 for performing storage management functions when operating in the normal operation state. When devices 44 comprise Flash devices, the storage management functions are sometimes referred to as “Flash management.” For example, the SSD controller may use the hibernation storage space for increasing the over-provisioning ratio, to serve as a binary cache, or for any other suitable purpose. The over-provisioning and binary cache examples are described in detail further below. These uses of the hibernation storage space are typically temporary in nature, since the SSD controller is usually requested to make the hibernation storage space available for storing the hibernation file upon entering hibernation. The embodiments described herein address mainly storage management (e.g., Flash management) functions. In alternative embodiments, however, the SSD controller may use the hibernation storage space for storing data or for any other suitable purpose when the host system operates in the normal state.

FIG. 2 is a diagram that schematically illustrates a hibernation storage space used for storage management during normal operation, in accordance with an embodiment of the present invention. As seen at the top of the figure, the overall memory space in devices 44 comprises multiple memory blocks 60. A certain portion of the total memory space is reserved as a hibernation storage space 64. The hibernation storage space may comprise any suitable number of pages or parts of pages, and may be distributed among memory blocks 60 in any suitable manner.

The bottom of FIG. 2 shows a portion 68 of hibernation storage space 64, which is used by SSD controller 40 for storage management functions. In some embodiments, SSD controller 40 uses all of space 64 for storage management. Alternatively, the SSD controller may use only part of the hibernation storage space for this purpose.

As explained above, the host processor reserves a certain set of logical addresses to serve as hibernation storage space 64, i.e., for storing the hibernation file. The physical storage location of the hibernation file in memory devices 44 may change over time. Portion 68, which is used for storage management, may also comprise a set of logical addresses whose corresponding physical storage locations may change over time.

SSD controller 40 may identify whether the host system is currently in the normal state or in the hibernation state, and/or whether the host system is currently entering or exiting the hibernation state. Moreover, the SSD controller may identify the logical addresses (e.g., LBAs) in which the hibernation-related information (e.g., hibernation file) is stored. These identification tasks can be performed based on suitable notifications from the host processor, or automatically regardless of any host notification. Several examples of such techniques are described below.

In some embodiments, SSD controller 40 identifies at least some of the (logical or physical) locations of the hibernation storage space automatically, i.e., without being notified of these locations by host processor 24. For example, the SSD controller may automatically identify the size and storage locations (e.g., LBAs) of a file named “HIBERFILE.SYS” that holds the hibernation-related information. The file name and attributes may change with the type of file system used by the host processor.

SSD controller 40 may identify the storage locations of the hibernation file HIBERFILE.SYS using various techniques. In an example embodiment, controller 40 first identifies the Master File Table (MFT) record corresponding to HIBERFILE.SYS in the root folder. The SSD controller may, for example, search exhaustively through the MFT records. This technique does not require support of NT File System (NTFS) features in the SSD controller, but on the other hand is relatively time-consuming. Alternatively, the SSD controller may open the root folder data and search this data for HIBERFILE.SYS. This technique is fast, but may require the SSD controller to support various NTFS features in order to parse the root folder data.

Having identified the MFT record corresponding to HIBERFILE.SYS, the SSD controller opens this record and parses its attached attributes. In some embodiments, the SSD controller verifies, using the record attributes, that the record in question is still valid and still references HIBERFILE.SYS (a precaution against a scenario in which the host decides to stop hibernation and lets a different file occupy this record space).

From the record attributes, the SSD controller finds the fragments (typically start/end cluster pairs) that specify the storage locations of the hibernation file HIBERFILE.SYS. In some cases, the file is not fragmented, in which case a single start/end pair would indicate the storage location of the entire file. In other cases, the file is fragmented into several fragments, in which case the MFT record would contain the descriptions of all the start/end cluster pairs specifying the file's storage locations. In some cases, the file is heavily fragmented, such that the MFT record is too small to hold all the relevant location descriptions. In these cases, the MFT record typically contains an attribute that indicates a cluster range holding the full list of start/end cluster pairs. In any of these cases, the SSD controller analyzes the content of the MFT record in order to find the storage locations assigned to the hibernation file.

In alternative embodiments, the host processor may store the hibernation file using a dedicated “WRITE_HIBERNATE_DATA” command, which is different from the write command used for storing user data. In these embodiments, the SSD controller can identify the storage locations (e.g., LBAs) that are written using the “WRITE_HIBERNATE_DATA” command, and conclude that these locations correspond to the hibernation storage space. Having identified the location of the hibernation storage space, the SSD controller may use at least part of this space for storage management. Alternatively, the SSD controller may receive a notification from the host processor, indicating the logical addresses in which the hibernation file is stored.

SSD Operation Method Description

FIG. 3 is a flow chart that schematically illustrates a method for operating SSD 32, in accordance with an embodiment of the present invention. In this method, the SSD controller releases logical storage space (LBAs in the present example) that is used by the hibernation file for other purposes when the host system is not in hibernation. In the present embodiment, the SSD controller automatically detects situations in which the host system prepares to enter the hibernation state, by detecting multiple write commands to the hibernation storage space. Such multiple write commands are assumed to indicate that the host processor has started to copy the content of RAM 28 into the hibernation file. Upon detecting this event, the SSD controller switches to storage using a high-speed configuration, in order to speed-up entry to hibernation.

The method of FIG. 3 begins with SSD controller 40 initializing following boot of the host system, at an initialization step 70. At this stage, the host system is assumed to be in the hibernation state. Thus, the SSD controller initializes an internal flag denoted HIBERNATION FLAG to TRUE.

The SSD controller checks whether the host system has ended the hibernation state, at a hibernation checking step 74. In an example embodiment, the SSD controller examines the content of memory devices 44, finds the file system tree, and in particular identifies the hibernation file HIBERFILE.SYS. The SSD then examines the data in the first cluster of the hibernation file, and checks whether this data is all-zeros or not. (Typically, examining the first four bytes of the first cluster is sufficient for determining whether the hibernation file is valid or not.) If the beginning of first cluster is non-zero, then the hibernation file is valid, meaning that the host system is still in the hibernation state. If the beginning of the first cluster is all-zero, the SSD controller concludes that the host processor has marked the hibernation file as invalid, and therefore the host system is no longer in the hibernation state. Alternatively, the SSD controller may decide whether or not hibernation has ended based on a notification from the host processor, or using any other suitable method.

If the SSD controller concludes that the host system exited the hibernation state and entered the normal state, the SSD controller releases at least some of the logical addresses (LBAs in the present example) that were occupied by the (now invalid) hibernation file, at a LBA releasing step 78. The released LBAs can be used by the SSD controller for other purposes, e.g., for serving as additional over-provisioning space.

In some embodiments, the SSD controller determines which LBAs are occupied by the hibernation file by examining the file system information stored in memory devices 44. In alternative embodiments, the SSD controller is notified by the host processor as to the LBAs used for storing the hibernation file. The SSD controller typically finds the physical storage locations in memory devices 44 that correspond to these LBAs.

In some embodiments, the SSD controller may find the LBAs used by the hibernation file at any other suitable time, not necessarily when exiting from hibernation. Upon releasing the hibernation file LBAs, the SSD controller sets the HIBERNATION FLAG to FALSE. If the SSD controller concludes, at step 74 above, that the host system is still in hibernation, then step 78 is skipped, i.e., the LBAs of the hibernation file are not released.

The SSD controller receives and executes a write command accepted from the host system, at a writing step 82. The SSD controller stores the data received in the write command in memory devices 44. This write command may be written to a LBA that is part of the hibernation storage space (i.e., to a LBA that is used by the hibernation file) or to a LBA that is outside the hibernation storage space. The SSD controller now checks whether the host system is in hibernation, at a state checking step 86. The SSD controller may determine the system state using any of the techniques described herein. If the host system is in hibernation, the method loops back to step 74 above.

If the host system is not in hibernation, the SSD controller evaluates a criterion for detecting whether the host system is currently preparing to enter the hibernation state. For this purpose, the SSD controller maintains a counter denoted N, which counts the number of write commands that are addressed to LBAs that belong to the hibernation storage space. If the SSD controller detects a certain number of such write commands, it concludes that the host processor has started backing-up the RAM content to the hibernation file. Upon detecting this event, the SSD controller switches to a high-speed programming configuration, in order to increase the speed at which the hibernation file is stored.

If step 86 concludes that the host system is not in hibernation, the SSD controller checks whether the LBA specified in the write command (received at step 82) is inside or outside the hibernation storage area, at a LBA checking step 90. If step 90 concludes that the write command was written into the hibernation storage area, the SSD controller reduces the over-provisioning overhead, at an over-provisioning reduction step 94. The SSD controller then increments N, at an incrementing step 98. If step 90 concludes that the write command was written outside the hibernation storage area, steps 94 and 98 are skipped.

The SSD controller checks whether the current value of N indicates that entry to hibernation has began, at an entry checking step 102. In an embodiment, the SSD controller compares N to a certain threshold and concludes that the host system is preparing to enter hibernation if N exceeds the threshold. In alternative embodiments, the SSD controller may use other techniques for detecting that the host processor has began storing the hibernation file. For example, the SSD controller may check whether one or more “WRITE_HIBERNATION_DATA” commands are accepted from the host processor. Further alternatively, any other suitable criterion can also be used.

If the SSD controller detects that the host system prepares to enter hibernation (i.e., is in the process of storing the hibernation file), the SSD controller begins storing data using a high-speed storage configuration, at a high-speed storage step 106. Storing the hibernation file at high speed is highly advantageous in many practical cases, such as when the host system enters hibernation because of low battery. Any suitable high-speed storage configuration can be used. In an example embodiment, the SSD controller normally stores data using multiple bits per cell (MLC), and at step 106 switches to store data using a single bit per cell (SLC). As another example, the SSD controller may begin storing data in parallel on a higher number of memory devices (e.g., dies) than the number of devices used for normal storage. As yet another example, the SSD controller may switch to storing data using a SLC cache, which is later copied to MLC storage.

The method then loops back to step 82 for receiving and executing subsequent write commands from the host system. If the current value of N does not indicate entry to hibernation, step 106 is skipped, and the method loops back directly to step 82.

Additional Embodiments and Variations

In some embodiments, when the SSD controller determines that the host system returns to the normal state (and assuming the hibernation-related information has already been read by the host processor) the SSD controller marks the hibernation-related information as invalid. In some embodiments, after host processor 24 retrieves the hibernation file from the SSD, SSD controller 40 receives from the host processor a command instructing it to invalidate the hibernation file. The command may comprise a dedicated command that is defined specifically for invalidating the hibernation file. Alternatively, the host processor may invalidate the hibernation file using a command that is also used for other purposes, such as a TRIM command. For example, the Advanced Technology Attachment (ATA) protocol supports a “ATA DATA SET MANAGEMENT (TRIM)” command that can be used for this purpose. Other protocols may support similar commands.

Typically, the SSD controller marks the hibernation-related information as invalid, and sends an acknowledgement to the host processor. In alternative embodiments, the SSD controller can identify the storage locations used by the hibernation-related information, and mark these locations as invalid without explicit instructions from the host processor. Such mechanism is feasible, for example, in file systems such as File Allocation Table (FAT), FAT32, New Technology File System (NTFS), EX2, or in any other suitable file system in which the hibernation file has detectable attributes or characteristics.

The SSD controller may decide whether the hibernation-related information is valid or invalid using any suitable method. For example, in some embodiments the hibernation file is stored as a linked list of LBAs. In this configuration, each LBA comprises a portion of the hibernation-related information, and a link to the next LBA. As noted above, the beginning of first cluster of the hibernation file is all-zero if the hibernation file is invalid, and not all-zero if the hibernation file is valid. Thus, by checking the value of the beginning of first cluster in the first LBA of the hibernation file, the SSD controller can determine whether the hibernation-related information is valid or not. Alternatively, any other suitable technique can be used.

In some embodiments, the SSD controller detects certain data that is not related to hibernation but was nevertheless stored in the hibernation storage space by the host operating system. This sort of data will typically not be marked as invalid upon readout of the hibernation file, and the SSD controller will treat it similarly to user data. The space occupied by such data is typically not used for management functions.

In some embodiments, SSD controller 40 stores and/or retrieves the hibernation file using programming/readout operations that are different from the operations used for storing and retrieving user data. These programming/readout operations are typically faster than the respective operations used for user data, and thus increase the speed of switching to and from hibernation. Other performance parameters, such as power consumption, may be compromised in these operations, in order to increase speed.

In some embodiments, SSD controller 40 compresses the hibernation-related information before storing it in the hibernation storage space. The host processor may not be aware of this compression. The compression enables the SSD controller to reduce the size of the reserved hibernation storage space, and thus free memory resources for storing user data or for any other purpose. In addition, the time needed to store and retrieve the hibernation file can be shortened considerably. In alternative embodiments, compression of the hibernation-related information can be performed by the host processor operating system. Since the content of RAM 28 typically comprises executable code and data, compression ratios on the order of 30-40% can be achieved, providing a corresponding reduction in memory utilization and storage/retrieval time.

As explained above, in some embodiments the SSD controller identifies the LBAs occupied by the hibernation file HIBERFILE.SYS by scanning the file system information of the host system as it is stored in memory devices 44, identifying the linked chain of LBAs that stores this file, and checking whether the beginning of the first cluster of the hibernation file is zero (examining the first four bytes will typically suffice to determine if the hibernation file is valid or not, since usually the first 512 bytes are set to zero when the file is invalid). In some embodiments, the SSD controller can use this technique in order to identify other files that were declared invalid by the host system's file system. Once identified, the memory space occupied by such files can be released.

Example Storage Management Functions Using the Hibernation Storage Space

As explained above, SSD controller 40 can use some or all of the hibernation storage space for performing storage management functions as well as for storing other kinds of data and for other purposes. For example, the SSD controller may use the hibernation storage space to increase the over-provisioning overhead of the SSD. Over-provisioning is a mechanism deployed in Flash devices and other analog memory cell devices due to the fact that (1) Data is written in the device page-by-page, (2) memory cells cannot be overwritten and need to be erased first, and (3) memory cells are erased in memory block units, each block comprising multiple pages.

When using over-provisioning, the actual physical memory size that is available for storing data is larger than the specified memory capacity (i.e., the size of the address space accessible to the host processor). The ratio between the actual physical capacity and the specified capacity is typically defined as the over-provisioning ratio. Consider, for example, a SSD that is operating at an over-provisioning ratio of 15% and is fully-programmed from the point of view of the host processor. In this scenario, each memory block in the SSD will be, on average, only 85% programmed. On average, 15% of each memory block will comprise invalid data or un-programmed memory cells.

In order to erase memory blocks and make them available for programming, the SSD controller copies valid data from partially-programmed blocks, so as to condense the data and clear memory blocks for erasure. This process is sometimes referred to as garbage collection. As can be appreciated, the SSD needs to perform a number of programming operations per each new page being programmed. The average number of programming operations per each new page (sometimes referred to as write amplification) increases as a function of the over-provisioning ratio. Thus, the over-provisioning ratio has a considerable impact on the achievable SSD programming throughput. This effect is particularly noticeable when the SSD is fully or nearly fully programmed.

In some embodiments, SSD controller 40 uses the hibernation storage space to increase the over-provisioning ratio of the SSD. In other words, during normal operation, there is no need to reserve memory space for hibernation-related information, and this space can be used as extra over-provisioning space. As a result, the SSD programming throughput can be significantly increased. When preparing to enter hibernation, the hibernation storage area can no longer be used for over-provisioning, and the over-provisioning ratio is reduced accordingly.

Additionally or alternatively, SSD controller 40 can use some or all of the hibernation storage space as a write cache memory. In these embodiments, SSD controller 40 accepts user data for storage from host processor 24, caches the user data temporarily in the hibernation storage space, and later copies the cached data to long-term storage locations outside the hibernation storage space. Write caching can be used in various ways to improve programming performance. Storage schemes that use write caching are described, for example, in U.S. patent application Ser. Nos. 12/186,867, 12/332,370, 12/551,567 and 12/579,430, which are assigned to the assignee of the present patent application and whose disclosures are incorporated herein by reference.

In some embodiments, the SSD controller caches the user data in the hibernation storage space using a storage configuration that is optimized for throughput, possibly at the expense of other performance parameters such as retention or density. Later, the SSD controller copies the cached data to its long-term storage locations outside the hibernation storage space. The SSD controller may store the data in the long-term storage locations using a different storage configuration, typically having lower throughput. The long-term storage configuration may be optimized for retention and/or density. For example, the SSD controller may cache the user data using only two programming levels per memory cell (i.e., at a density of one bit per cell), and later store the data using a higher number of programming levels per memory cell (i.e., at a density of more than one bit per cell). Alternatively, any other caching and/or long-term storage configuration can be used.

In some embodiments, the SSD controller uses the hibernation storage space for storing data, e.g., user data or management data, while the host system is not in hibernation. When the host system prepares to enter hibernation, the SSD controller vacates this storage space, e.g., by copying the data to other storage locations outside the hibernation storage space, or by compressing the data. The SSD controller vacates the storage space, for example, in response to a notification from the host system indicating entry to hibernation.

It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. 

The invention claimed is:
 1. A method for data storage, comprising: operating a host system alternately between a normal state and a hibernation state; reserving a hibernation storage space in a non-volatile storage device to store hibernation-related information in preparation for the host entering the hibernation state, wherein the non-volatile storage device includes memory blocks allocated as a user data storage space, over-provisioning memory, and the hibernation storage space; and allocating at least a portion of the hibernation storage space as over-provisioning memory during operation in the normal state, thereby allowing the over-provisioning memory to be used as a cache for valid data from partially-programmed memory blocks in a user data storage space subsequent to an erasure operation being performed on one or more locations of the user data storage space.
 2. The method according to claim 1, further comprising allocating at least another portion of the hibernation storage space as a cache, and caching user data accepted from the host system in the at least another portion of the hibernation storage space at a first data rate, and subsequently copying the cached user data to storage locations outside the hibernation storage space at a second data rate that is slower than the first data rate.
 3. The method according to claim 1, wherein reserving the hibernation storage space includes the host system allocating a set of storage locations of the user data storage space to serve as the hibernation storage space, and wherein copying valid data to the at least a portion of the hibernation storage space comprises identifying at least part of the storage locations in the set using a file holding the hibernation-related information in a file system of the host system.
 4. The method according to claim 3, further comprising, in preparation for entering the hibernation state, receiving the hibernation-related information from the host system using one or more dedicated hibernation write commands, wherein identifying the at least part of the storage locations in the set comprises detecting the storage locations written to using the dedicated hibernation write commands.
 5. The method according to claim 1, further comprising switching to a high-speed storage configuration for storing the hibernation-related information in response to detecting that the host system is preparing to enter the hibernation state.
 6. The method according to claim 5, wherein detecting that the host system is preparing to enter the hibernation state comprises detecting one of one or more dedicated hibernation write commands received from the host system, detecting one or more write commands to storage locations belonging to the hibernation storage space, or receiving a notification from the host system indicating a preparation to enter the hibernation state.
 7. The method according to claim 1, further comprising detecting that the host system is preparing to exit the hibernation state by one of detecting one or more read commands from storage locations belonging to the hibernation storage space, or receiving a notification from the host system indicating a preparation to exit the hibernation state.
 8. The method according to claim 1, further comprising writing user data at a first data rate, and in preparation for entering the hibernation state, writing the hibernation-related information to the hibernation storage space at a second data rate that is higher than the first data rate.
 9. The method according to claim 1, further comprising, in preparation for entering the hibernation state, compressing the hibernation-related information and storing the compressed hibernation-related information in the hibernation storage space.
 10. An apparatus comprising: a non-volatile memory including multiple memory blocks allocated as a user data storage space, over-provisioning memory, and the hibernation storage space; and a memory controller coupled to the non-volatile memory and configured to: reserve the hibernation storage space in the non-volatile memory to store hibernation-related information in preparation for a host system entering the hibernation state; and allocate at least a portion of the hibernation storage space as over-provisioning memory during operation in the normal state, thereby allowing the over-provisioning memory to be used as a cache for valid data from partially-programmed memory blocks in a user data storage space subsequent to an erasure operation being performed on one or more locations of the user data storage space.
 11. The apparatus according to claim 10, wherein the memory controller is configured to allocate at least another portion of the hibernation storage space as a cache, and to cache user data accepted from the host system in the at least another portion of the hibernation storage space, and to subsequently copy the cached user data to storage locations outside the hibernation storage space.
 12. The apparatus according to claim 10, wherein the memory controller is further configured to allocate a set of storage locations of the user data storage space to serve as the hibernation storage space, and wherein the memory controller is configured to identify at least part of the storage locations in the set using a file holding the hibernation-related information in a file system of the host system.
 13. The apparatus according to claim 12, wherein the memory controller is further configured to identify the storage locations in the set by receiving a notification from the host system indicative of the set of storage locations.
 14. The apparatus according to claim 10, wherein the memory controller is further configured to, in preparation for entering the hibernation state, receive the hibernation-related information from the host system via one or more dedicated hibernation write commands, wherein the memory controller is further configured to identify the storage locations in the set using the dedicated hibernation write commands.
 15. The apparatus according to claim 10, wherein the memory controller is configured to store the hibernation-related information using a high-speed storage configuration in response to detecting that the host system is preparing to enter the hibernation state.
 16. The apparatus according to claim 15, wherein the memory controller is configured to detect that the host system is preparing to enter the hibernation state by at least one of: detecting one or more dedicated hibernation write commands received from the host system, detecting one or more write commands to storage locations belonging to the hibernation storage space, or receiving a notification from the host system indicating a preparation to enter the hibernation state.
 17. The apparatus according to claim 10, wherein the memory controller is configured to determine that the host system is preparing to exit the hibernation state in response to one of: receiving one or more read commands from storage locations belonging to the hibernation storage space, or receiving a notification from the host system indicating a preparation to exit the hibernation state.
 18. The apparatus according to claim 10, wherein the memory controller is configured to copy valid data from the partially-programmed memory blocks in the user data storage space to the at least the portion of the hibernation storage space only in response to verifying that the hibernation-related information is invalid.
 19. The apparatus according to claim 10, wherein, subsequent to the host system exiting from the hibernation state and retrieving the hibernation-related information from the non-volatile storage device, the memory controller is configured to mark the hibernation-related information as invalid.
 20. The apparatus according to claim 10, wherein the memory controller is configured to write user data at a first data rate, and to write the hibernation-related information to the hibernation storage space at a second data rate that is higher than the first data rate. 